FIG. 1 is a graph showing resistance of a gate line as a function of reduction of a design rule.
Referring to FIG. 1, the horizontal axis indicates a line width of the gate line in nm, and the vertical axis indicates the resistance of the gate line in Ω. When the line width of the gate line is reduced, the resistance of the gate line-increases rapidly. In order to reduce the rapidly increasing resistance of the gate line due to an increase in integration density and the reduction of the design rule in a semiconductor device, the resistivity of a material used for forming the gate line can be reduced.
Polysilicon, fabricated by a low pressure chemical vapor deposition (LP CVD) method, has been used in a gate structure in which a conductive thin layer is deposited on a gate oxide layer, because polysilicon is stable, can be easily bonded to a thin layer, can be readily deposited at room temperature, and can be readily patterned by an etching process. However, polysilicon can be inappropriate for a high density integrated circuit since polysilicon has a relatively high electrical resistance even though the electrical conductivity can be increased by injecting a dopant into polysilicon.
In view of the advantages of polysilicon, various structures have been developed to reduce the electrical resistance of polysilicon. Examples of developed structures include a polyside structure in which a metal silicide, for example, WSi2, TiSi2, TaSi2, MoSi2, is deposited on polysilicon; a salicide structure in which a metal and silicon are annealed; a structure that includes a pure metal silicide or a nitride; and a structure that includes a metal.
In some polyside structures, such as, a WSix structure, problematic peeling of a thin layer and problematic abnormal oxidation in a subsequent insulation layer deposition process can occur. The peeling of a thin layer is related to the adhesion force and stress of the thin layer, and the abnormal oxidation is related to an atom ratio of tungsten to silicon and a deposition condition in a subsequent insulation layer deposition process. Also, the electrical resistance of a polyside structure is determined by the resistance of WSix, and increases due to effects caused by grain boundaries and interfaces in addition to a bulk resistance with the reduction of a line width. A specific resistance of a CVD WSix obtained using commercially available equipment can be approximately 40 to 80 μΩ-cm, so there can be a limit in applying this structure to a high density integrated circuit.
In some embodiments, a metal gate has been introduced to further increase device speed. A most commonly used material in this regard is tungsten. In a method of forming tungsten using a CVD method, fluoride (F) atoms can affect the purity of the tungsten. With regard to a gate structure, since a step coverage may not be important, a physical vapor deposition (PVD) method can be used. However, if tungsten directly contacts a gate oxide layer, tungsten atoms, which are heavy, can damage a surface of the gate oxide layer when the tungsten atoms are deposited, or there is a risk of forming WOx at an interface between tungsten and the gate oxide layer during a subsequent process. Thus, a barrier thin layer, for example, a titanium nitride, may be used.
When a W thin layer is formed on a TiN thin layer that is used as a barrier thin layer, the W thin layer grows in a pillar shape along a minute grain structure of TiN, and thus, the specific resistance of the W thin layer may be increased.